US 12,462,070 B2
Software assisted acceleration in cryptographic queue processing
Shijie Che, Markham (CA); and Wentao Xu, Markham (CA)
Assigned to ATI Technologies ULC, Markham (CA)
Filed by ATI Technologies ULC, Markham (CA)
Filed on Dec. 28, 2021, as Appl. No. 17/563,900.
Prior Publication US 2023/0205935 A1, Jun. 29, 2023
Int. Cl. G06F 21/72 (2013.01); G06F 12/128 (2016.01); G06F 12/14 (2006.01); G06F 16/00 (2019.01); G06F 21/60 (2013.01); H04L 15/16 (2006.01); H04L 29/06 (2006.01); H04L 29/08 (2006.01)
CPC G06F 21/72 (2013.01) 17 Claims
OG exemplary drawing
 
1. A processor comprising:
circuitry configured to:
receive a plurality of commands, each comprising a cryptographic function;
generate an issue group comprising at least two commands of the plurality of commands that have a data dependency between them or target shared source data;
issue a first command of the issue group to execute a cryptographic function;
issue a second command of the plurality of commands to execute a cryptographic function, in response to the second command being in the issue group; and
issue a third command instead of the second command, in response to the second command not being in the issue group and the third command being a next in-order command after the first command.