US 12,461,890 B2
Reconfigurable processor circuit architecture
Paul L. Master, Sunnyvale, CA (US); Steven K. Knapp, Soquel, CA (US); Raymond J. Andraka, North Kings Town, RI (US); Alexei Beliaev, Campbell, CA (US); Martin A Franz, Sunnyvale, CA (US); Rene Meessen, San Francisco, CA (US); and Frederick Curtis Furtek, Menlo Park, CA (US)
Assigned to Cornami, Inc., Dallas, TX (US)
Filed by Cornami, Inc., Dallas, TX (US)
Filed on Jan. 18, 2024, as Appl. No. 18/415,958.
Application 18/415,958 is a continuation of application No. 18/092,247, filed on Dec. 31, 2022, granted, now 11,907,157.
Application 18/415,958 is a continuation of application No. 17/967,173, filed on Oct. 17, 2022, granted, now 11,977,509.
Application 18/092,247 is a continuation of application No. 17/967,173, filed on Oct. 17, 2022, granted, now 11,977,509.
Application 17/967,173 is a continuation of application No. 17/015,973, filed on Sep. 9, 2020, granted, now 11,494,331, issued on Nov. 8, 2022.
Claims priority of provisional application 62/899,025, filed on Sep. 11, 2019.
Claims priority of provisional application 62/898,452, filed on Sep. 10, 2019.
Prior Publication US 2024/0152486 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 15/78 (2006.01); G06F 5/01 (2006.01); G06F 7/487 (2006.01); G06F 7/50 (2006.01); G06F 7/52 (2006.01); G06F 7/523 (2006.01); G06F 7/544 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/54 (2006.01); G06F 15/80 (2006.01); H03K 19/21 (2006.01)
CPC G06F 15/80 (2013.01) [G06F 5/01 (2013.01); G06F 7/487 (2013.01); G06F 7/50 (2013.01); G06F 7/52 (2013.01); G06F 7/523 (2013.01); G06F 7/5443 (2013.01); G06F 9/30098 (2013.01); G06F 9/3856 (2023.08); G06F 9/4881 (2013.01); G06F 9/54 (2013.01); H03K 19/21 (2013.01); G06F 2207/382 (2013.01)] 32 Claims
OG exemplary drawing
 
1. A reconfigurable processor circuit comprising:
a first interconnection network;
a second interconnection network;
a processor coupled to the first interconnection network; and
a plurality of computational cores arranged in an array, the plurality of computational cores coupled to the first interconnection network and to the second interconnection network, the second interconnection network configured to couple adjacent computational cores of the plurality of computational cores, each computational core comprising:
a memory circuit; and
a reconfigurable arithmetic circuit comprising:
at least one input reordering queue;
a multiplier shifter and combiner network coupled to the at least one input reordering queue, the multiplier shifter and combiner network comprising:
a shifter circuit; and
a plurality of series-coupled adder circuits coupled to the shifter circuit;
an accumulator circuit;
at least one control logic circuit coupled to the multiplier shifter and combiner network and to the accumulator circuit; and
a compare circuit coupled to the at least one input reordering queue, the compare circuit configured to perform modulo counting.