US 12,461,887 B1
PCIe retimer with reduced power low latency mode
Tao Yu, Milpitas, CA (US); Junqing Sun, Fremont, CA (US); Tianchen Luo, Milpitas, CA (US); Sanket Shah, Milpitas, CA (US); and Don Barnetson, Campbell, CA (US)
Assigned to Credo Technology Group Limited, Grand Cayman (KY)
Filed by Credo Technology Group Limited, George Town (KY)
Filed on Aug. 22, 2024, as Appl. No. 18/812,627.
Int. Cl. G06F 13/40 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/4291 (2013.01) [G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A retimer comprising:
an upstream interface having an upstream receiver configured to convert a downlink signal into a downlink symbol stream;
a downstream interface having a downstream transmitter configured to provide a transmit signal representing the downlink symbol stream;
core circuitry having:
a downstream path configured to convey the downlink symbol stream from the upstream receiver to the downstream transmitter, the downstream path having a receive clock domain component, a core clock domain component, and a transmit clock domain component; and
a downstream bypass path configurable to convey the downlink symbol stream from the upstream receiver to the downstream transmitter without any core clock domain components; and
a controller configured to disable a clock signal for the transmit clock domain component of the downstream path when the downstream bypass path is enabled.