US 12,461,877 B2
3D stacked device having improved data flow
Dinesh D. Gaitonde, Fremont, CA (US); Aashish Tripathi, Hyderabad (IN); Ashit Debnath, Hyderabad (IN); Davis Boyd Moore, Longmont, CO (US); Maithilee Rajendra Kulkarni, Santa Clara, CA (US); and Abhishek Kumar Jain, Ghaziabad (IN)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Apr. 14, 2023, as Appl. No. 18/134,994.
Prior Publication US 2024/0345977 A1, Oct. 17, 2024
Int. Cl. G06F 13/40 (2006.01)
CPC G06F 13/4059 (2013.01) [G06F 13/4068 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a 3D stacked device having a plurality of semiconductor chips stacked vertically on each other, the method comprising:
providing a first plurality of tiles in a first semiconductor chip of the plurality of semiconductor chips;
providing a second plurality of tiles in a second semiconductor chip of the plurality of semiconductor chips;
assigning each of the first plurality of tiles to a corresponding one of the second plurality of tiles to form tile-to-tile pairs;
determining a minimized sum of bus delays among the tile-to-tile pairs;
and
electrically coupling each of the first plurality of tiles to the corresponding one of the second plurality of tiles through buses based on the assignments.