| CPC G06F 13/382 (2013.01) [G06F 13/4004 (2013.01)] | 12 Claims |

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1. An apparatus, comprising:
a circuit that includes:
repeater circuitry having first and second inputs and first and second outputs;
a processing circuit having first and second outputs;
a first logic circuit having an output and first and second inputs, wherein the first input of the first logic circuit is coupled to the second output of the processing circuit, and the second input of the first logic circuit is coupled to the second output of the repeater circuitry;
a second logic circuit having an output and first and second inputs, wherein the first input of the second logic circuit is coupled to the output of the first logic circuit;
a timer circuit having an output and first and second inputs, wherein the first input of the timer circuit is coupled to the output of the first logic circuit, the second input of the timer circuit is coupled to the output of the second logic circuit, and the output of the timer circuit is coupled to the second input of the second logic circuit; and
a third logic circuit having an output and first and second inputs, wherein the first input of the third logic circuit is coupled to the first output of the processing circuit, the second input of the third logic circuit is coupled to the output of the timer circuit, and the output of the third logic circuit is coupled to the second input of the repeater circuitry;
wherein the repeater circuitry includes a squelch detector that detects downstream packets.
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