US 12,461,872 B2
Semiconductor device for performing data reduction for processing arrays
William Peter Ehrett, Austin, TX (US); Anthony Gutierrez, Bellevue, WA (US); Vedula Venkata Srikant Bharadwaj, Bellevue, WA (US); Karthik Ramu Sangaiah, Bellevue, WA (US); Prachi Shukla, Santa Clara, CA (US); Sriseshan Srikanth, Austin, TX (US); Ganesh Dasika, Austin, TX (US); and John Kalamatianos, Boxborough, MA (US)
Assigned to Advanced Micro Devices, Inc., Austin, TX (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 30, 2023, as Appl. No. 18/217,079.
Prior Publication US 2025/0004963 A1, Jan. 2, 2025
Int. Cl. G06F 13/36 (2006.01)
CPC G06F 13/36 (2013.01) [G06F 2213/0056 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
one or more connectors for connecting the semiconductor device to a processing element array in a stacked arrangement, wherein the processing element array includes a plurality of processing elements that are configured to generate a plurality of processing results,
a plurality of reduction operators configured to perform one or more data reduction operations on the plurality of processing results generated by the plurality of processing elements on the processing element array and generate a plurality of data reduction results, and
an interconnect coupled to the plurality of reduction operators and the one or more connectors.