US 12,461,868 B2
Input/output sequencer instruction set processing
Kinyue Szeto, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 15, 2023, as Appl. No. 18/510,574.
Application 18/510,574 is a continuation of application No. 17/531,140, filed on Nov. 19, 2021, granted, now 11,853,237.
Prior Publication US 2024/0086344 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/12 (2006.01); G06F 13/16 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 2213/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device;
an input/output (IO) instruction memory; and
a processing device, operatively coupled with the memory device via a signal communication bus, to perform operations comprising:
retrieving a single IO instruction of a plurality of IO instructions from the IO instruction memory, the single IO instruction comprising a first number of bits;
generating a temporal sequence of two or more IO vectors based on the single IO instruction, each IO vector in the temporal sequence comprising a second number of bits and used to drive a plurality of IO signals on the signal communication bus to control communication signals to the memory device over successive time periods, wherein the second number of bits is greater than the first number of bits, and wherein each IO vector in the temporal sequence comprises a first subset of bits in a different state from a corresponding first subset of bits in a previous IO vector in the temporal sequence; and
causing the plurality of IO signals, based on the temporal sequence of IO vectors, to be driven on the signal communication bus to the memory device, wherein the plurality of IO signals comprises a number of signals equal to the second number of bits of each IO vector in the temporal sequence.