US 12,461,861 B2
Two-stage address translation
Richard Roy Grisenthwaite, Cambridge (GB)
Assigned to Arm Limited, Cambridge (GB)
Appl. No. 18/711,242
Filed by Arm Limited, Cambridge (GB)
PCT Filed Apr. 28, 2022, PCT No. PCT/GB2022/051073
§ 371(c)(1), (2) Date May 17, 2024,
PCT Pub. No. WO2023/099860, PCT Pub. Date Jun. 8, 2023.
Claims priority of application No. 2117274 (GB), filed on Nov. 30, 2021.
Prior Publication US 2025/0021487 A1, Jan. 16, 2025
Int. Cl. G06F 12/1009 (2016.01); G06F 9/455 (2018.01); G06F 12/14 (2006.01)
CPC G06F 12/1009 (2013.01) [G06F 9/45558 (2013.01); G06F 12/1458 (2013.01); G06F 12/1491 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/651 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
processing circuitry to process instructions in one of a plurality of execution states associated with different levels of privilege; and
memory management circuitry to translate a target virtual address specified by a memory access request into a target physical address indicative of a memory system location to be accessed in response to the memory access request; in which:
the memory management circuitry is configured to support two-stage address translation based on a stage-1 translation table structure comprising stage-1 translation table entries and a stage-2 translation table structure comprising stage-2 translation table entries, where a mapping from the target virtual address to the target physical address depends on a stage-1 address mapping and a stage-2 address mapping, the stage-1 address mapping comprising a mapping from the target virtual address to a target intermediate address specified by a corresponding stage-1 translation table entry corresponding to the target virtual address, and the stage-2 address mapping comprising a mapping from the target intermediate address to the target physical address specified by a corresponding stage-2 translation table entry corresponding to the target intermediate address;
the memory management circuitry is configured to perform permission checking for the memory access request based at least on stage-2 access permission information specified by the corresponding stage-2 translation table entry, the stage-2 access permission information having an encoding specifying whether a memory region corresponding to the target intermediate address has a partially-read-only permission indicating that write requests to the memory region corresponding to the target intermediate address, issued when the processing circuitry is in a predetermined execution state of the plurality of execution states, are permitted for a restricted subset of write request types but prohibited for write request types other than the restricted subset, the restricted subset of write request types comprising a metadata-updating write request generated by the memory management circuitry to update access tracking metadata in translation table entries; and
the memory management circuitry is configured to reject the memory access request in response to determining that the memory access request is a write request issued in the predetermined execution state, the stage-2 access permission information specifies that the memory region corresponding to the target intermediate address has the partially-read-only permission, and the memory access request is a write request type other than the restricted subset of write request types.