US 12,461,860 B2
Physical address based set partitioning
Subbarao Palacharla, San Diego, CA (US); Hiral Nandu, South San Francisco, CA (US); George Patsilaras, San Diego, CA (US); Simon Peter William Booth, San Diego, CA (US); Rakesh Kumar Gupta, San Diego, CA (US); and Kedar Bhole, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Nov. 28, 2023, as Appl. No. 18/522,049.
Claims priority of provisional application 63/500,560, filed on May 5, 2023.
Prior Publication US 2024/0370376 A1, Nov. 7, 2024
Int. Cl. G06F 12/0888 (2016.01); G06F 12/0864 (2016.01)
CPC G06F 12/0888 (2013.01) [G06F 2212/604 (2013.01)] 29 Claims
OG exemplary drawing
 
1. An apparatus for data processing, comprising:
at least one memory; and
at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory, the at least one processor, individually or in any combination, is configured to:
configure an address range in a cache, wherein the address range is associated with data allocations for the cache;
obtain a request to access data in the cache, wherein the request to access the data includes an address in the cache that maps to a set index in a plurality of set indexes, wherein an address value for the set index corresponds to a portion of the address in the cache;
select, based on the address value of the set index, an updated address value for the set index, wherein the updated address value is associated with an updated address within the address range in the cache, and wherein the updated address value corresponds to a portion of the updated address in the cache; and
allocate the data in the request to the updated address value for the set index.