| CPC G06F 12/0855 (2013.01) [G06F 12/0246 (2013.01); G06F 2212/2022 (2013.01)] | 27 Claims |

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1. A host for a memory device comprising:
a bus interface coupled to a bus, the bus configured to carry commands as packets to and from a memory controller of the memory device;
background operation circuitry configured to set a background operation enable flag, to enable a background operation by the memory device on a physical block of memory cells of the memory device by sending a command to the memory controller through the bus, wherein the host is coupled to the memory device through a bus for memory access, wherein the memory controller operates the background operation independently of the host, to receive an operation completed notification from the memory device to indicate that the memory device has completed performing the background operation on the physical block of memory cells, to clear the background operation enable flag in response to the receiving the operation completion notification, and to send a command to the memory controller to clear the enabling of the background operation in response to the receiving the operation completed notification; and
memory access command circuitry configured to receive a memory access command from a higher layer of a computing system after setting the background operation enable flag, wherein the memory access command concerns reading or writing data to the memory device coupled to the host, to initiate a wait at the host for the memory access command in response to the receiving after setting the background operation enable flag, and to send the memory access command through the bus to the memory device in response to the receiving the operation completed notification.
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