| CPC G06F 12/0815 (2013.01) [G06F 9/3842 (2013.01); G06F 12/0811 (2013.01); G06F 12/0855 (2013.01); G06F 12/0862 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/507 (2013.01)] | 7 Claims |
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1. A processor comprising:
a plurality of core circuits each having an arithmetic operation circuit executing an issued instruction, a load store unit that executes an issued memory access instruction, a level 1 cache, and a re-order buffer that controls an instruction execution completion process of the arithmetic operation circuit and the load store unit; and
a cache unit having a plurality of caches from a level 2 cache to a level N cache, N being an integer equal to or greater than 3,
wherein the level 1 cache has a move-in buffer that has a plurality of entries in which a memory access instruction that results in a cache miss in the level 1 cache is stored,
wherein the move-in buffer
issues a normal memory request, which performs memory access of the memory access instruction that results in the cache miss, to the level 2 cache, the normal memory request being issued from the level 2 cache to the level N cache serially, and
receives a normal data response that has coherency-secured data from any one of the level 2 cache to the level N cache in which the normal memory request result in a cache hit,
wherein, when the normal memory request is issued to the level 2 cache,
a pseudo memory request that performs the memory access is issued to a level 3 cache in a case where N is 3, or
the pseudo memory request is issued to the level 3 cache to the level N cache in parallel in a case where N is 4 or more,
wherein the move-in buffer receives a pseudo data response that has coherency-unsecured data from any one cache in which the pseudo memory request result in a cache hit, and
wherein the re-order buffer
executes a normal instruction execution completion process in response to the normal data response,
executes a pseudo instruction execution completion process in response to the pseudo data response, and,
when the pseudo data response is a failure, rewinds the arithmetic operation circuit, which speculatively executed an instruction after the memory access instruction that result in the cache miss in response to the pseudo instruction execution completion process, back to a state before the speculative execution.
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