US 12,461,855 B2
System and method for memory bandwidth reduction using a programmable cache line
Chrysa Kokkala, Patras (GR); Nikolaos Mitas, Patras (GR); Iakovos Stamoulis, Patras (GR); and Georgios Keramidas, Patras (GR)
Assigned to Think Silicon Research and Technology Single Member S.A., Rion Achaias (GR)
Appl. No. 18/068,938
Filed by Think Silicon Research and Technology Single Member S.A., Rion Achaias (GR)
PCT Filed Dec. 12, 2022, PCT No. PCT/GR2022/000069
§ 371(c)(1), (2) Date Dec. 20, 2022,
PCT Pub. No. WO2024/127046, PCT Pub. Date Jun. 20, 2024.
Prior Publication US 2025/0291721 A1, Sep. 18, 2025
Int. Cl. G06F 12/00 (2006.01); G06F 12/02 (2006.01); G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 12/0223 (2013.01); G06F 2212/1021 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method for memory bandwidth reduction using a programmable cache line, comprising:
generating an instruction to render a modified texture based on a modification of a texture, the texture stored as a plurality of lines in a memory, each line addressable by a unique address;
determining an amount of data to read from a first line of a texture based on the modification;
configuring a programmable cache line to read into a cache at least the determined amount of data from a unique address corresponding to the first line; and
storing at least a portion of the determined amount of data in a first line of a framebuffer.