US 12,461,842 B2
Systems, apparatus, and methods to debug accelerator hardware
Martin-Thomas Grymel, Leixlip (IE); David Bernard, Kilcullen (IE); Martin Power, Dublin (IE); Niall Hanrahan, Galway (IE); and Kevin Brady, Newry (GB)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 16, 2023, as Appl. No. 18/487,490.
Application 18/487,490 is a continuation of application No. 17/483,521, filed on Sep. 23, 2021, granted, now 11,829,279.
Prior Publication US 2024/0118992 A1, Apr. 11, 2024
Int. Cl. G06F 11/00 (2006.01); G06F 11/277 (2006.01); G06F 11/30 (2006.01); G06F 11/362 (2025.01); G06N 3/04 (2023.01)
CPC G06F 11/3652 (2013.01) [G06F 11/277 (2013.01); G06F 11/3075 (2013.01); G06F 11/3656 (2013.01); G06N 3/04 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A system, comprising:
a neural network accelerator to perform execution of a neural network and to generate output signals;
a debugger to:
receive the output signals from the neural network accelerator,
receive a breakpoint configuration signal that indicates a breakpoint condition,
detect an occurrence of the breakpoint condition based on an output signal generated by the neural network accelerator, and
halt an operation of the neural network accelerator that is associated with the output signal; and
a memory to receive, through the debugger, one or more output signals generated by the neural network accelerator and to store data in the one or more output signals,
wherein data transfer between the neural network accelerator and the memory is through one or more memory transactions, a memory transaction comprises a memory address and a data item to be written to the memory address, and the breakpoint condition is specific to one or more memory addresses or one or more data items in the one or more memory transactions.