US 12,461,822 B2
Mechanism to enhance link bandwidth in interconnects
Prakhar Srivastava, Lucknow (IN); Santhosh Reddy Akavaram, Hyderabad (IN); Chintalapati Bharath Sai Varma, Hyderabad (IN); Ravi Kumar Sepuri, Hyderabad (IN); and Khushboo Kumari, Noida (IN)
Assigned to Qualcomm Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Mar. 4, 2024, as Appl. No. 18/594,913.
Prior Publication US 2025/0278336 A1, Sep. 4, 2025
Int. Cl. G06F 11/14 (2006.01)
CPC G06F 11/1402 (2013.01) [G06F 2201/86 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for operating an interconnection between chiplets, comprising:
transmitting or receiving data over a multimodule data communication link that uses a first plurality of link modules to provide data transmit lanes and data receive lanes;
retraining a failed link module in the first plurality of link modules while one or more other link modules in the first plurality of link modules are active and available for transmitting or receiving data;
reconfiguring the multimodule data communication link to operate using one or more remaining active link modules in the first plurality of link modules to provide the data transmit lanes and the data receive lanes and without the failed link module while the failed link module is being retrained; and
reconfiguring the multimodule data communication link to use the first plurality of link modules for transmitting or receiving the data after the failed link module has been successfully retrained.