US 12,461,819 B2
Apparatus and methods for memory data integrity within die architectures
Subham Panda, Balasore (IN); Nileshkumar Chandrakantbhai Motawala, Surat (IN); Radhakrishna Mugada, Hyderabad (IN); Sri Ananda Sai Jannabhatla, Hyderabad (IN); Muzaffaruddin Mohammed, Hyderabad (IN); Jyothi Ramidi, Hyderabad (IN); and Venkatesh Petnikota, Kurnool (IN)
Assigned to Qualcomm Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Oct. 19, 2023, as Appl. No. 18/490,478.
Prior Publication US 2025/0130898 A1, Apr. 24, 2025
Int. Cl. G06F 11/10 (2006.01); G06F 11/00 (2006.01); H03M 13/00 (2006.01)
CPC G06F 11/1076 (2013.01) [H03M 13/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A die comprising:
a row decoding logic coupled to a memory array and configured to:
receive address data; and
generate a row selection signal;
a row error count buffer configured to maintain an error count for each row of the memory array; and
a processor configured to write data stored at a first memory row of the memory array to a second memory row of the memory array.