US 12,461,816 B2
Electronic system for monitoring error of address
Jin Ho Jeong, Icheon-si (KR); Saeng Hwan Kim, Icheon-si (KR); and Mun Seon Jang, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Feb. 26, 2024, as Appl. No. 18/587,385.
Claims priority of application No. 10-2023-0139062 (KR), filed on Oct. 17, 2023.
Prior Publication US 2025/0123923 A1, Apr. 17, 2025
Int. Cl. G06F 11/10 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/1004 (2013.01); G06F 11/1016 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An electronic system comprising:
a controller configured to output a command, external row addresses, and external column addresses, receive a flag signal, and output the flag signal to a host; and
a semiconductor device configured to correct an error of internal data output from a memory cell selected based on the command, the external row addresses having different combinations, and the external column addresses having different combinations to output error-corrected internal data as data, and output the flag signal that is enabled when correcting the error in the internal data a set number of times,
wherein the semiconductor device is configured to enable the flag signal when the error in the internal data output by the external column addresses having different combinations in one combination of the external row addresses is corrected the set number of times.