US 12,461,811 B2
Error type indication
Steffen Buch, Munich (DE)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 18, 2021, as Appl. No. 17/529,925.
Claims priority of provisional application 63/121,744, filed on Dec. 4, 2020.
Prior Publication US 2022/0179733 A1, Jun. 9, 2022
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/10 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 26 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a decoder configured to detect one or more errors in a codeword;
a first logic gate coupled with the decoder and configured to perform a first logical OR operation on a first set of bits output from the decoder, the first set of bits representing error flags for a set of parity bits included in the codeword; and
a second logic gate coupled with the decoder and configured to perform a second logical OR operation on a second set of bits output from the decoder, the second set of bits representing error flags for a set of data bits included in the codeword.