US 12,461,781 B2
Low power inference engine pipeline in a graphics processing unit
Vidhya Krishnan, Folsom, CA (US); Chien-Wei Li, Portland, OR (US); Ben J. Ashbaugh, Folsom, CA (US); Durgaprasad Bilagi, Folsom, CA (US); and Pattabhiraman K, Bangalore (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2021, as Appl. No. 17/559,352.
Prior Publication US 2023/0195519 A1, Jun. 22, 2023
Int. Cl. G06F 1/26 (2006.01); G06F 1/32 (2019.01); G06F 1/3293 (2019.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06N 20/00 (2019.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01)
CPC G06F 9/4893 (2013.01) [G06F 1/3293 (2013.01); G06F 9/505 (2013.01); G06N 20/00 (2019.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a compute workload at a software interface for a graphics processor, the graphics processor including multiple hardware processing engines, the multiple hardware processing engines including a first compute engine and a second compute engine, the second compute engine having a lower power consumption relative to the first compute engine;
determining a target engine of the multiple hardware processing engines to which the compute workload is to be dispatched;
generating a list of hardware commands to dispatch to the target engine;
tagging the list of hardware commands with an indicator of the target engine; and
submitting a tagged list of hardware commands to the target engine to enable execution of the compute workload.