US 12,461,775 B2
Controller with caching and non-caching modes
Abhijeet Ashok Chachad, Plano, TX (US); Timothy David Anderson, University City, TX (US); and David Matthew Thompson, Dallas, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jan. 12, 2024, as Appl. No. 18/411,763.
Application 18/411,763 is a continuation of application No. 17/981,591, filed on Nov. 7, 2022, granted, now 11,907,753.
Application 17/981,591 is a continuation of application No. 16/882,329, filed on May 22, 2020, granted, now 11,494,224, issued on Nov. 8, 2022.
Prior Publication US 2024/0152385 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/46 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/448 (2018.01); G06F 9/48 (2006.01); G06F 9/54 (2006.01); G06F 11/30 (2006.01); G06F 12/0804 (2016.01); G06F 12/0811 (2016.01); G06F 12/0813 (2016.01); G06F 12/0817 (2016.01); G06F 12/0831 (2016.01); G06F 12/0855 (2016.01); G06F 12/0871 (2016.01); G06F 12/0888 (2016.01); G06F 12/0891 (2016.01); G06F 12/12 (2016.01); G06F 12/121 (2016.01); G06F 13/16 (2006.01)
CPC G06F 9/467 (2013.01) [G06F 9/30047 (2013.01); G06F 9/30079 (2013.01); G06F 9/30098 (2013.01); G06F 9/30101 (2013.01); G06F 9/30189 (2013.01); G06F 9/3867 (2013.01); G06F 9/4498 (2018.02); G06F 9/4881 (2013.01); G06F 9/544 (2013.01); G06F 11/3037 (2013.01); G06F 12/0811 (2013.01); G06F 12/0813 (2013.01); G06F 12/0824 (2013.01); G06F 12/0828 (2013.01); G06F 12/0831 (2013.01); G06F 12/0855 (2013.01); G06F 12/0871 (2013.01); G06F 12/0888 (2013.01); G06F 12/0891 (2013.01); G06F 12/12 (2013.01); G06F 13/1668 (2013.01); G06F 12/0804 (2013.01); G06F 12/121 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/621 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a level-one (L1) cache memory;
a level-two (L2) cache memory coupled to the L1 cache memory;
a level-two (L2) cache controller coupled to the L2 cache memory;
a level-three (L3) cache memory coupled to the L2 cache controller, wherein the L3 cache memory includes a first address region; and
a configuration register configured to store a configuration value associated with the first address region of the L3 cache memory,
wherein the L2 cache controller is configured to:
receive a read request directed to the first address region of the L3 cache memory;
provide the read request to the L3 cache memory;
receive data associated with the read request from the L3 cache memory; and
determine whether to store the data in the L2 cache memory based on the configuration value associated with the first address region of the L3 cache memory.