US 12,461,747 B2
Processor, method, device and storage medium for data processing
Yuhui Cao, Beijing (CN); Yunfeng Shi, Beijing (CN); and Jian Wang, Beijing (CN)
Assigned to BEIJING YOUZHUJU NETWORK TECHNOLOGY CO., LTD., Beijing (CN)
Filed by Beijing Youzhuju Network Technology Co., Ltd., Beijing (CN)
Filed on Dec. 12, 2024, as Appl. No. 18/979,402.
Application 18/979,402 is a continuation of application No. PCT/CN2023/098716, filed on Jun. 6, 2023.
Claims priority of application No. 202210674857.6 (CN), filed on Jun. 14, 2022.
Prior Publication US 2025/0110742 A1, Apr. 3, 2025
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/3016 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30043 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A processor, comprising:
an instruction decoder configured to decode at least one target instruction to obtain at least one source storage location in a memory for reading at least one to-be- processed data, at least one target storage location in the memory for writing at least one processed result and at least one vector operation to be performed on the at least one to-be-processed data, each target instruction involving a target opcode indicating a vector operation, a source operand specifying at least a source storage location in the memory, and a target operand specifying at least a target storage location in the memory; and
an arithmetic logic unit coupled to the instruction decoder and the memory and configured to:
read the at least one to-be-processed data from the at least one source storage location of the memory;
perform, on the at least one to-be-processed data, at least one arithmetic logic operation associated with the at least one vector operation specified by the at least one target instruction; and
write at least one processed result of the at least one to-be-processed data to the at least one target storage location of the memory,
wherein the at least one target instruction at least comprises a one-hot code conversion instruction, wherein the source operand of the one-hot code conversion instruction specifies a given index value of the to-be-processed data within a storage space of the memory, the source storage location of the to-be-processed data being indicated by the given index value, the target operand of the one-hot code conversion instruction specifies that the target storage location comprises a target vector mask (VM) register, and
the arithmetic logic unit is configured to perform, based on the one-hot code conversion instruction:
converting the value of the to-be-processed data at the source storage location based on the given index value to a one-hot code; and
storing the one-hot code into the target VM register.