US 12,461,746 B2
Converting a stream of data using a lookaside buffer
Joseph Raymond Michael Zbiciak, San Jose, CA (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on May 6, 2024, as Appl. No. 18/655,454.
Application 15/429,205 is a division of application No. 14/331,986, filed on Jul. 15, 2014, granted, now 9,606,803, issued on Mar. 28, 2017.
Application 18/655,454 is a continuation of application No. 17/748,954, filed on May 19, 2022, granted, now 11,977,892.
Application 17/748,954 is a continuation of application No. 16/861,347, filed on Apr. 29, 2020, granted, now 11,347,510, issued on May 31, 2022.
Application 16/861,347 is a continuation of application No. 16/206,091, filed on Nov. 30, 2018, granted, now 10,649,775, issued on May 12, 2020.
Application 16/206,091 is a continuation in part of application No. 15/429,205, filed on Feb. 10, 2017, granted, now 10,162,641, issued on Dec. 25, 2018.
Claims priority of provisional application 61/846,148, filed on Jul. 15, 2013.
Prior Publication US 2024/0296050 A1, Sep. 5, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/02 (2006.01); G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 9/345 (2018.01); G06F 9/38 (2018.01); G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01); G06F 5/06 (2006.01)
CPC G06F 9/3016 (2013.01) [G06F 9/30014 (2013.01); G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30098 (2013.01); G06F 9/30112 (2013.01); G06F 9/30145 (2013.01); G06F 9/32 (2013.01); G06F 9/345 (2013.01); G06F 9/3802 (2013.01); G06F 9/383 (2013.01); G06F 9/3867 (2013.01); G06F 11/00 (2013.01); G06F 11/1048 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 5/06 (2013.01); G06F 9/30043 (2013.01); G06F 9/3822 (2013.01); G06F 11/10 (2013.01); G06F 2205/067 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first memory configured to store a first data stream that includes a first set of data elements;
a processor core configured to provide an instruction to read the first data stream;
a memory controller coupled between the first memory and the processor core that includes:
an address generator configured to generate a set of addresses associated with the first data stream;
an interface coupled to the first memory to retrieve the first set of data elements from the first memory using the set of addresses; and
a second memory configured to store a table, wherein the memory controller is configured to:
determine a second set of data elements of a second data stream by:
querying the table based on the first set of data elements by:
 determining a respective address for each data element of the first set of data elements; and
 querying the table based on the respective address to determine a respective data element of the second set of data elements; and
provide the second set of data elements to the processor core.