US 12,461,744 B2
Streaming engine with early exit from loop levels supporting early exit loops and irregular loops
Joseph Zbiciak, San Jose, CA (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jul. 31, 2023, as Appl. No. 18/361,985.
Application 18/361,985 is a continuation of application No. 17/163,639, filed on Feb. 1, 2021, granted, now 11,714,646.
Application 17/163,639 is a continuation of application No. 15/636,669, filed on Jun. 29, 2017, granted, now 10,908,901, issued on Feb. 2, 2021.
Prior Publication US 2023/0385063 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/34 (2018.01); G06F 9/32 (2018.01); G06F 9/38 (2018.01); G06F 12/0875 (2016.01)
CPC G06F 9/30065 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/34 (2013.01); G06F 9/3016 (2013.01); G06F 9/325 (2013.01); G06F 9/3802 (2013.01); G06F 9/381 (2013.01); G06F 12/0875 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a processor core that includes an instruction decoder;
a memory control circuit coupled to the processor core that includes an address generator circuit and a set of registers coupled to the address generator circuit; and
a cache memory coupled to the memory control circuit and configured to store a set of data;
wherein the instruction decoder is configured to:
based on a first instruction:
initiate generation, using the memory control circuit, of a set of addresses associated with the set of data, wherein:
the generation of the set of addresses uses a set of nested loops; and
the set of registers includes a respective register for each loop of the set of nested loops; and
initiate retrieval of the set of data from the cache memory using the set of addresses; and
cause a value to be stored in the respective register of a first loop based on a second instruction specifying the first loop, wherein the second instruction is a break instruction; and
wherein the memory control circuit is configured to interrupt the generation of the set of addresses based on the value stored in the respective register.