US 12,461,713 B2
MAC processing pipelines, circuitry to configure same, and methods of operating same
Frederick A. Ware, Los Altos Hills, CA (US); and Cheng C. Wang, San Jose, CA (US)
Assigned to Analog Devices, Inc., Wilmington, MA (US)
Filed by Analog Devices, Inc., Wilmington, MA (US)
Filed on Feb. 28, 2022, as Appl. No. 17/683,284.
Claims priority of provisional application 63/156,263, filed on Mar. 3, 2021.
Prior Publication US 2022/0283779 A1, Sep. 8, 2022
Int. Cl. G06F 7/544 (2006.01); G06F 9/38 (2018.01)
CPC G06F 7/5443 (2013.01) [G06F 9/3893 (2013.01); G06F 2207/3884 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a plurality MAC processors, interconnected into a linear pipeline, configurable to process input data during a plurality of execution cycles of an execution sequence, wherein each MAC processor of the plurality of the MAC processors includes:
a multiplier circuit to (i) receive first input data at a first input and (ii) receive multiplier weight data at a second input, (iii) multiply first input data by multiplier weight data to generate product data, and (iv) output the product data,
an accumulator circuit, coupled to the multiplier circuit of the associated MAC processor, to (i) receive accumulation data at a first input, (ii) receive the product data output by the associated multiplier circuit, (iii) add the accumulation data and the product data output by the associated multiplier circuit to generate second accumulation data, and (iv) output the second accumulation data via an output of the accumulation circuit, and
an accumulation data path to couple the output of the accumulation circuit of the associated MAC processor to the first input thereof;
a plurality of rotate input data paths, wherein each rotate input data path couples two sequential MAC processors of the linear pipeline including the first input of the multiplier circuit of a first MAC processor of sequential MAC processors to the first input of the multiplier circuit of the immediately following MAC processor of the associated sequential MAC processors of the linear pipeline; and
wherein each rotate input data path is configurable to provide rotate input data from a first MAC processor of sequential MAC processors of the linear pipeline to the immediately following MAC processor of the associated sequential MAC processors thereby forming a serial circular path, including the plurality of MAC processors of the linear pipeline, via the plurality of rotate input data paths.