US 12,461,712 B2
In-memory near-data approximate acceleration
Nam Sung Kim, Champaign, IL (US); Hadi Esmaeilzadeh, Atlanta, GA (US); and Amir Yazdanbakhsh, Atlanta, GA (US)
Assigned to The Board of Trustees of the University of Illinois, Urbana, IL (US); and Georgia Tech Research Corporation, Atlanta, GA (US)
Appl. No. 17/285,409
Filed by The Board of Trustees of the University of Illinois, Urbana, IL (US)
PCT Filed Oct. 14, 2019, PCT No. PCT/US2019/056068
§ 371(c)(1), (2) Date Apr. 14, 2021,
PCT Pub. No. WO2020/081431, PCT Pub. Date Apr. 23, 2020.
Claims priority of provisional application 62/745,688, filed on Oct. 15, 2018.
Prior Publication US 2021/0382691 A1, Dec. 9, 2021
Int. Cl. G06F 7/544 (2006.01); G06F 1/03 (2006.01); G06F 7/527 (2006.01); G06N 3/04 (2023.01); G11C 7/10 (2006.01); G06F 17/17 (2006.01)
CPC G06F 7/5443 (2013.01) [G06F 1/03 (2013.01); G06F 7/527 (2013.01); G06N 3/04 (2013.01); G11C 7/1012 (2013.01); G06F 17/17 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A random access memory comprising:
a plurality of memory banks, wherein the plurality of memory banks comprise four bank-groups each with four of the memory banks;
a plurality of arithmetic units, each associated with one or more of the memory banks, wherein the arithmetic units are configured to perform operations on respective inputs and to provide respective results of the operations, and wherein the arithmetic units are configured for parallel operation, wherein each of the memory banks comprises two half-banks, and wherein a group of four arithmetic units from the plurality of arithmetic units is dedicated to two pairs of the two half-banks; and
a memory controller configured to receive instructions, from a processor, regarding locations within the memory banks from which to obtain the respective inputs or in which to write respective outputs based on the respective results.