| CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
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1. A non-volatile memory device, comprising:
a control circuit configured to connect to an array of non-volatile memory cells, the array having a NAND architecture including a block comprising a plurality of NAND strings having memory cells connected along word lines and each connected to a corresponding bit line, the block having a plurality of sub-divisions, the NAND strings of each sub-division connected to the corresponding bit line through a corresponding one or more first select gates layers and a corresponding plurality of second select gate layers, the second select gate layers between the first select gate layers and the bit lines, the control circuit configured to program the memory cells of a selected one of the sub-divisions, where, to program the memory cells of the selected sub-division, the control circuit is configured to:
bias select gates of the first select gate layers corresponding to the selected sub-division to be on;
bias select gates of the first select gate layers corresponding to un-selected sub-divisions to be off;
bias select gates of a first of the second select gate layers of all of the sub-divisions at a first voltage level;
bias select gates of a second of the second select gate layers corresponding to the selected sub-division at a second voltage level; and
bias select gates of the second of the second select gate layers corresponding to one or more of the un-selected sub-divisions to be off,
the second voltage configured to turn on the select gates of the second select gate layers, the first voltage level being higher than the second voltage level, and the second of the second select gate layers being between the first of the second select gate layers and the first select gate layers.
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