US 12,461,691 B2
Memory device background operations
Marco Redaelli, Munich (DE); and Gianluca Coppola, Saviano (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 13, 2024, as Appl. No. 18/603,746.
Claims priority of provisional application 63/504,597, filed on May 26, 2023.
Prior Publication US 2024/0393978 A1, Nov. 28, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/061 (2013.01); G06F 3/0616 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
one or more components, implemented at least partially in hardware, configured to:
receive a background operation command, from a host device, that indicates for the memory device to initiate a background operation for a memory of the memory device,
wherein the background operation command includes an optimization indicator, an idle time indicator, and a power-off time indicator; and
initiate the background operation in accordance with the background operation command.