US 12,461,690 B2
Memory system with dummy read before patrol read
Kazukuni Kitagaki, Sagamihara Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Aug. 31, 2023, as Appl. No. 18/459,376.
Claims priority of application No. 2022-202493 (JP), filed on Dec. 19, 2022.
Prior Publication US 2024/0201903 A1, Jun. 20, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit, comprising:
a first interface circuit configured to be connected to a control device;
a second interface circuit configured to be connected to a memory chip; and
a controller configured to:
generate and transfer a first command sequence for commanding a dummy read operation on a storage region of the memory chip via the second interface circuit before any patrol read operation is executed on the storage region of the memory chip, the patrol read operation being initiated based on a request from the control device received via the first interface circuit and instructed to the memory chip via the second interface circuit, the first command sequence being generated independently and transferred separately from the request from the control device.