US 12,461,684 B2
Scheduling processing-in-memory transactions
Alexandru Dutu, Kirkland, WA (US); and Sooraj Puthoor, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 29, 2022, as Appl. No. 18/148,000.
Prior Publication US 2024/0220160 A1, Jul. 4, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 13/16 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0607 (2013.01); G06F 3/0656 (2013.01); G06F 3/0658 (2013.01); G06F 13/1673 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory of a memory module;
a processing-in-memory component of the memory module; and
a memory controller disposed outside the memory module, the memory controller including a transaction header buffer and configured to:
receive a transaction header, from a host, for a transaction to be executed by the processing-in-memory component using data stored in the memory;
add the transaction header to the transaction header buffer; and
send an acknowledgement message to the host responsive to detecting that scheduling the transaction does not conflict with a different transaction based on information stored in the transaction header buffer; or
send a negative acknowledgment message to the host responsive to detecting that scheduling the transaction conflicts with the different transaction, based on information stored in the transaction header buffer.