US 12,461,681 B2
Fine-grained clocking and clock distribution in low power double data rate physical layer interface
Pouya Najafi Ashtiani, Toronto (CA); Anwar Parvez Kashem, Sudbury, MA (US); Kapil Acharya, Bangalore (IN); and Mahanth Kumar Gurram, Bengaluru (IN)
Assigned to Advanced Micro Devices, Inc, Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed by Advanced Micro Devices, Inc, Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed on Dec. 20, 2023, as Appl. No. 18/390,853.
Prior Publication US 2025/0208788 A1, Jun. 26, 2025
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/061 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device;
a memory controller; and
a physical layer interface that connects the memory device and the memory controller, the physical layer interface including:
an active first-in-first-out buffer configured to receive commands from the memory controller; and
an on-demand first-in-first-out buffer configured to be selectively enabled by the active first-in-first-out buffer to handle a data payload received from the memory controller, wherein the active first-in-first-out buffer is configured to enable or disable the on-demand first-in-first-out buffer by communicating an enable or disable command to the on-demand first-in-first-out buffer.