| CPC G06F 3/0635 (2013.01) [G06F 3/061 (2013.01); G06F 3/0683 (2013.01)] | 10 Claims |
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1. A many-core definable distributed shared storage structure, comprising:
an internal data bus system, comprising a transverse bidirectional data line, a longitudinal bidirectional data line, and a processor core storage access bus;
a plurality of routing units, each arranged at an intersection of the transverse bidirectional data line and the longitudinal bidirectional data line, and configured to transmit data;
a plurality of processor cores, each connected to a corresponding routing unit via a corresponding network interface unit;
a plurality of network interface units, each connected to a corresponding routing unit through a corresponding processor core storage access bus; and
a plurality of memory modules, each connected to a corresponding routing unit directly,
wherein the plurality of the memory modules constitute a storage structure system inside a many-core processor,
wherein each network interface unit comprises: a configuration package parsing unit, a data packet assembling/parsing unit, and a routing table,
wherein the configuration package parsing unit is configured to parse a configuration package acquired from the routing unit, wherein the configuration package is parsed by: judging an operation type by a packet header; extracting address information and data information in the configuration package; and combining the operation type, the address information and the data information, to obtain and output a routing configuration instruction and a routing control instruction to the routing table, wherein
the routing configuration instruction comprises the address information, the data information and a first writing signal;
the routing control instruction comprises memory module grouping flag information, memory module ping pong reading and writing control information, and a second writing signal,
wherein the data packet assembling/parsing unit is responsible for data format conversion between the processor core and the corresponding routing unit connected thereto, to obtain a valid data by parsing a data packet acquired from the corresponding routing unit; and
wherein the data packet assembling/parsing unit is configured to
convert (1) and (2) to a network-on-chip transmittable data packet: (1) a reading and writing data output from the processor cores; and (2) a physical coordinate position of a destination memory module acquired from the routing table, and
output the network-on-chip transmittable data packet to the corresponding routing unit,
wherein the packet header of the data packet comprises the physical coordinate position of the destination memory module acquired from the routing table,
wherein the routing table is configured to support judgment and query, in response to the address signal output from the processor core, of a physical coordinate position of a destination memory module corresponding to said address signal, and to provide said physical coordinate position for the data packet assembling/parsing unit;
wherein all fields in the routing table are written or changed in line with the routing configuration instruction; and
wherein a routing control field in the routing table is written or changed in line with the routing control instruction.
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