US 12,461,670 B2
Enhanced power management of flash memory device
Santhosh Reddy Akavaram, Hyderabad (IN); Prakhar Srivastava, Lucknow (IN); Chintalapati Bharath Sai Varma, Hyderabad (IN); and Sridhar Anumala, Hyderabad (IN)
Assigned to Qualcomm Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Mar. 12, 2024, as Appl. No. 18/602,637.
Prior Publication US 2025/0291499 A1, Sep. 18, 2025
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
12. A method comprising:
selecting, at a host device that is coupled to a flash memory device, an interrupt level that indicates a threshold background operation status of a set of background operation statuses;
writing the selected interrupt level to a register at the flash memory device to indicate, to the flash memory device, which of the set of background operation statuses are permissible sources of an interrupt from the flash memory device to the host device; and
transitioning, by the host device, to a low-power mode of operation based on having written the selected interrupt level to the register at the flash memory device.