US 12,461,669 B2
Memory device background operation management for low host battery
Pratibind Kumar Jha, Hyderabad (IN); Manish Garg, Hyderabad (IN); Ashwini Pandey, Muzaffarpur (IN); and Abhishek Ghosh, Kolkata (IN)
Assigned to Qualcomm Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 22, 2024, as Appl. No. 18/584,516.
Prior Publication US 2025/0272010 A1, Aug. 28, 2025
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0634 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A host device, comprising:
one or more memories; and
one or more processors, coupled to the one or more memories, configured to:
detect that the host device has a low battery status using a comparison of a battery level of the host device to a low battery threshold; and
provide, in association with detecting that the host device has the low battery status, a low battery status indication to a memory device via a status register to cause one or more background operations of the memory device to be deferred or unexecuted while the status register indicates the low battery status indication, wherein a first value of a bit of the status register indicates to the memory device that the low battery status is not present, and a second value of the bit of the status register indicates to the memory device that the low battery status is present and is used to cause the one or more background operations of the memory device to be deferred or unexecuted.