US 12,461,668 B2
Scheme for data entry insertion in a sparsely populated data structure
Leon Zlotnik, Camino, CA (US); and Brian Toronyi, Boulder, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 2, 2024, as Appl. No. 18/431,743.
Claims priority of provisional application 63/444,462, filed on Feb. 9, 2023.
Prior Publication US 2024/0272811 A1, Aug. 15, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
writing a plurality of data entries in a first memory bank that comprises a portion of a data structure that is stored across a plurality of memory banks;
determining, for a subsequent data entry, that the subsequent data entry has a value that is greater than a first data entry among the plurality of data entries in the first memory bank and less than a second data entry among the plurality of data entries in the first memory bank;
writing the subsequent data entry to an address location in a second memory bank of the plurality of memory banks that is between a lowermost address location and an uppermost address location of the second memory bank and in a row that spans the plurality of memory banks, wherein the first data entry among the plurality of data entries in the first memory bank or the second data entry among the plurality of data entries in the first memory bank are in the row that spans the plurality of memory banks; and
storing, in the data structure, a first bit corresponding to the address location in the second memory bank to which the subsequent data entry was written.