US 12,461,661 B2
Dynamic block categorization to improve reliability and performance in memory sub-system
Sandeep Reddy Kadasani, Meridian, ID (US); Pitamber Shukla, San Jose, CA (US); Scott Anthony Stoller, Boise, ID (US); and Niccolo' Righetti, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 2, 2024, as Appl. No. 18/624,657.
Application 18/624,657 is a continuation of application No. 17/867,204, filed on Jul. 18, 2022, granted, now 11,972,114.
Prior Publication US 2024/0248616 A1, Jul. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/064 (2013.01); G06F 3/0653 (2013.01); G06F 3/0688 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device comprising a set of blocks; and
a processing device coupled to the memory device, the processing device configured to perform operations comprising:
obtaining a set of threshold voltage distribution width measurements for a block in the set of blocks;
assigning the block to a group among multiple groups of blocks based on the set of threshold voltage distribution width measurements;
determining an endurance estimate for the block based on an endurance category assigned to the group, the determining of the endurance estimate comprising determining an estimated number of program/erase cycles during which the block is able to store data reliably based on the endurance category; and
managing one or more parameters of the block based on the endurance estimate.