US 12,461,660 B2
Data block refresh during read access
Luca Porzio, Casalnuovo (IT); Ting Luo, Santa Clara, CA (US); Ciro Feliciano, Casandrino (IT); and Giuseppe D'Eliseo, Caserta (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 8, 2023, as Appl. No. 18/504,985.
Claims priority of provisional application 63/427,353, filed on Nov. 22, 2022.
Prior Publication US 2024/0168654 A1, May 23, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 12/1009 (2016.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/1009 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
one or more memory devices; and
one or more controllers coupled with the one or more memory devices and configured to cause the apparatus to:
read data from a first block of non-volatile memory cells of a memory system;
determine whether the first block is associated with a first block type in accordance with reading the data, wherein the first block type comprises a production state awareness (PSA) block in accordance with the data being written to the first block prior to packaging the one or more memory devices in the memory system;
transmit the data in accordance with determining whether the first block is associated with the first block type; and
write the data to a second block of non-volatile memory cells of the memory system in accordance with determining that the first block is associated with the first block type.