US 12,461,650 B2
Address translation metadata compression in memory devices
Brian Toronyi, Boulder, CO (US); and Scheheresade Virani, Frisco, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 16, 2024, as Appl. No. 18/636,783.
Application 18/636,783 is a continuation of application No. 17/895,696, filed on Aug. 25, 2022, granted, now 12,001,678.
Prior Publication US 2024/0264743 A1, Aug. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/1009 (2016.01)
CPC G06F 3/0608 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 12/1009 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, wherein the processing device is configured to:
receive a memory access request specifying a logical address of a data item and a memory access operation to be performed with respect to the data item;
identify, in an address translation table, an address translation table entry referenced by the logical address;
determine a truncated physical address specified by the address translation table entry; and
perform the memory access operation using a computed physical address derived from the truncated physical address and a predefined number of bits of the logical address, wherein the predefined number of bits is specified by a configuration parameter associated with the memory device.