US 12,461,584 B2
Optimal ram layout for power consumption
Jean Francois Deschenes, Ste-Marthe-sur-le-lac (CA); and Cedric Migliorini, Roxboro (CA)
Assigned to Silicon Laboratories Inc., Austin, TX (US)
Filed by Silicon Laboratories Inc., Austin, TX (US)
Filed on Mar. 25, 2024, as Appl. No. 18/615,510.
Prior Publication US 2025/0298459 A1, Sep. 25, 2025
Int. Cl. G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 1/3296 (2019.01)
CPC G06F 1/3275 (2013.01) [G06F 1/3296 (2013.01)] 18 Claims
OG exemplary drawing
 
9. A device, comprising:
a processing unit;
a nonvolatile memory;
a data memory device, comprising a plurality of banks wherein power to each bank is independently controlled; and
a memory manager, wherein the memory manager is configured to:
copy instructions from the nonvolatile memory to a first portion of the memory device previously designated by a linker;
receive memory requirements from user level software and based on those memory requirements, perform an initialization process, wherein the initialization process comprises:
allocating memory for data buffers which do not need to be retained during deep sleep mode in a second portion of the memory device; and
servicing memory reservations from user level software after the copying and allocating are completed; wherein memory that is reserved is disposed in a third portion located between the first portion and the second portion.