US 12,461,583 B2
PHY lanes disabling for power efficiency
Amir Segev, Meiter (IL); and Shay Benisty, Beer Sheva (IL)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on Aug. 25, 2023, as Appl. No. 18/455,958.
Prior Publication US 2025/0068226 A1, Feb. 27, 2025
Int. Cl. G06F 1/3234 (2019.01); G06F 13/40 (2006.01)
CPC G06F 1/3253 (2013.01) [G06F 13/4068 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
determine that one or more lanes of a physical connection (PHY) is unused;
change a state of the one or more lanes of the PHY to an unconnected state from an unused state; and
change the state of the one or more lanes of the PHY back to the unused state, wherein the controller comprises a plurality of unactive lanes controllers (ULCs), wherein the one or more lanes comprises a plurality of lanes, and wherein a number of ULCs is equal to one less than a number of lanes of the plurality of lanes.