| CPC G06F 1/324 (2013.01) [G06F 1/3206 (2013.01)] | 19 Claims |
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1. An apparatus, comprising:
processor circuitry;
power monitor circuitry configured to generate activity information based on activity of different portions of the processor circuitry during operation of the processor circuitry;
clock circuitry configured to provide a clock signal to the processor circuitry;
machine learning circuitry configured to predict a future power state of the processor circuitry based on inputs that include the activity information, wherein the machine learning circuitry:
is configured to implement a multi-level decision structure that includes nodes at multiple hierarchical levels;
includes delay stages configured to propagate the activity information from multiple time intervals for the different portions of the processor circuitry, prior to providing the activity information as input to the multi-level decision structure;
includes mapping circuitry configured to assign respective outputs of the delay stages to node inputs of nodes of the multi-level decision structure; and
includes node evaluation circuitry configured to process, based on the mapped outputs of the delay stages, nodes from the multiple hierarchical levels of the multi-level decision structure, including to evaluate, at least partially in parallel: whether first delayed activity information from a first delay stage meets a first threshold for a first node in a first level and whether second delayed activity information from a second delay stage meets a second threshold for a second node in a second level; and
control circuitry configured to, in response to the machine learning circuitry predicting that the future power state of the processor circuitry falls within a set of one or more target predicted power states, control the clock circuitry to reduce a frequency of the clock signal provided to the processor circuitry.
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