US 12,461,553 B2
Clock driver, operating method thereof, memory device including clock driver, and memory system
Bumsoo Lee, Suwon si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 28, 2023, as Appl. No. 18/476,508.
Claims priority of application No. 10-2023-0009259 (KR), filed on Jan. 25, 2023.
Prior Publication US 2024/0248511 A1, Jul. 25, 2024
Int. Cl. G06F 1/12 (2006.01); G06F 1/08 (2006.01)
CPC G06F 1/12 (2013.01) [G06F 1/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock driver comprising:
a differential buffer configured to output a differential amplified clock signal pair in which differential amplified clock signals thereof oscillate in phases opposite to each other during a clock operation period, and saturate to different respective levels during a clock interruption period, based on a differential external clock signal pair in which differential external clock signals thereof oscillate in phases opposite to each other during the clock operation period and have a certain logic level during the clock interruption period; and
a signal coupler configured to generate a differential internal clock signal pair in which differential internal clock signals thereof oscillate in phases opposite to each other to levels higher and lower than a first reference level during the clock operation period, and each saturates to a level lower than the first reference level during the clock interruption period, based on the differential amplified clock signal pair, and configured to output a chip enable signal based on the differential internal clock signal pair, to a memory chip.