US 12,461,312 B2
Cladding structure in the back end of line of photonics chips
Ryan Sporer, Mechanicville, NY (US); Karen Nummy, Newburgh, NY (US); Keith Donegan, Saratoga Springs, NY (US); Thomas Houghton, Marlboro, NY (US); Yusheng Bian, Ballston Lake, NY (US); Takako Hirokawa, Ballston Lake, NY (US); and Kenneth Giewont, Hopewell Junction, NY (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Jun. 6, 2022, as Appl. No. 17/805,686.
Prior Publication US 2023/0393340 A1, Dec. 7, 2023
Int. Cl. G02B 6/30 (2006.01); G02B 6/12 (2006.01); G02B 6/132 (2006.01)
CPC G02B 6/30 (2013.01) [G02B 6/12 (2013.01); G02B 6/132 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) chip comprising:
a substrate;
an optical component above the substrate;
an active layer above the substrate;
a transistor on the active layer, the transistor includes a source or drain region;
a contact structure on the source or drain region;
a first connection level above the substrate, the first connection level includes the optical component, the transistor, the contact structure, and a first cladding structure, wherein the optical component is covered by the first cladding structure;
a second connection level on the first connection level, the second connection level includes a conductive line, the conductive line is disposed directly on the contact structure in the first connection level;
a third connection level on the second connection level;
a fourth connection level on the third connection level, the third connection level and the fourth connection level include an interlayer dielectric material;
a second cladding structure directly above the optical component, the second cladding structure having at least a section within the second connection level, the second cladding structure is directly on the first cladding structure, wherein the second cladding structure includes a material different from the interlayer dielectric material in the third and the fourth connection levels;
a photonics region above the substrate, the photonics region includes an edge coupler section and a waveguide section, wherein the optical component is positioned in the photonics region;
a third cladding structure on the second cladding structure, the third cladding structure is positioned in the photonics region, wherein the third cladding structure is positioned within the edge coupler section and not present in the waveguide section, and the second cladding structure extends laterally across the edge coupler section and the waveguide section; and
a logic region above the substrate, wherein the transistor, the contact structure, and the conductive line are positioned in the logic region.