US 12,461,151 B2
Method and system for testing blocks within device under test (DUT) using reconfigurable test logic
Manickam Muthiah, Shrewsbury, MA (US); Karthikeyan Keelapandal Sundaram, Chennai (IN); and Razi Abdul Rahim, Willowbrook, IL (US)
Assigned to HCL America Inc.
Filed by HCL America Inc., Sunnyvale, CA (US)
Filed on Jun. 14, 2023, as Appl. No. 18/209,534.
Prior Publication US 2024/0418778 A1, Dec. 19, 2024
Int. Cl. G01R 31/319 (2006.01); G01R 31/3183 (2006.01)
CPC G01R 31/31917 (2013.01) [G01R 31/318314 (2013.01); G01R 31/31908 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method for simultaneously testing multiple Device Under Test (DUT) internal blocks, the method comprising:
receiving, by a reconfigurable internal buffer of a DUT, an input stimulus corresponding to at least one of a plurality of DUT internal blocks within the DUT via a set of configuration registers, wherein the input stimulus corresponds to a test case;
selecting, via a control register, one or more DUT internal blocks from the plurality of DUT internal blocks to perform testing based on the input stimulus, wherein selecting the one or more DUT internal blocks comprises:
enabling via control bits, at least one multiplexer associated with the one or more DUT internal blocks;
sending, by the reconfigurable internal buffer and selectively routing, via the control register through at least one multiplexer, to a DUT internal block of the one or more DUT internal blocks, at least one of:
the input stimulus; or
a DUT output generated by a preceding DUT internal block;
testing the one or more DUT internal blocks based on the corresponding input stimulus; and
generating, by each of the one or more DUT internal blocks, a corresponding output in response to testing.