US 12,461,150 B2
Testing circuit
Yu-Lun Wan, Hsinchu (TW); Bor-Yueh Liu, Hsinchu (TW); Chen-Yuan Kao, Hsinchu (TW); and Ting-Yu Chen, Hsinchu (TW)
Assigned to Global Unichip Corporation, Hsinchu (TW); and Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Global Unichip Corporation, Hsinchu (TW); and Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 15, 2023, as Appl. No. 18/510,616.
Prior Publication US 2025/0155503 A1, May 15, 2025
Int. Cl. G01R 31/3185 (2006.01); G01R 31/317 (2006.01)
CPC G01R 31/318577 (2013.01) [G01R 31/31727 (2013.01); G01R 31/318536 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A testing circuit, comprising:
a clock cone, divided into a plurality of fan-out partitions operated in the same clock domain;
a plurality of shift register chains, configured to shift out a series of test signals, each shift register chain comprises a number of registers with the same amount of the fan-out partitions; and
a control circuit, connected to the clock cone and the plurality of shift register chains for receiving the series of test signals and an enable signal, the control circuit being configured to control all of the fan-out partitions according to the series of test signals and the enable signal,
wherein each test signal is a one-hot signal which has a random bit with the value of 1,
wherein each bit of the test signal is used to turn on or turn off of a corresponding one of the fan-out partitions, and the enable signal corresponds to a maximum number of the fan-out partitions that are turned on for testing.