US 12,461,147 B1
Reducing voltage drooping in a microelectronic chip
Hagen Schmidt, Tuebingen (DE); Andreas H. A. Arp, Nufringen (DE); Knut Schuenemann, Weil im Schoenbuch (DE); and Simon Büchsenstein, Stuttgart (DE)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jun. 5, 2024, as Appl. No. 18/733,984.
Claims priority of application No. 2406291 (GB), filed on May 6, 2024.
Int. Cl. G01R 31/3185 (2006.01); G06F 1/30 (2006.01)
CPC G01R 31/318552 (2013.01) [G06F 1/305 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer implemented method for reducing voltage drooping in a microelectronic chip, the method comprising:
using at least two local clock buffers to be fed with data by latches, wherein the at least two local clock buffers are triggered by a base clock signal;
separating a scan data launch clock from a capture clock with a variable time delay depending on a delay of a succeeding scan path of the latches, wherein the scan data launch clock and the capture clock are based on the base clock signal;
analyzing and categorizing the latches against the time delay into dedicated buffer group categories; and
assigning the at least two local clock buffers to the latches within the dedicated buffer group categories.