US 12,461,146 B2
Analog phase selection test system
Andreas Johannes Köllmann, Rosengarten (DE); and Ulrich Moehlmann, Moisburg (DE)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Sep. 13, 2022, as Appl. No. 17/943,288.
Prior Publication US 2024/0085476 A1, Mar. 14, 2024
Int. Cl. G01R 31/317 (2006.01); G01R 25/00 (2006.01); G01R 31/319 (2006.01); G01R 31/3193 (2006.01); H03K 5/156 (2006.01); H03K 5/19 (2006.01)
CPC G01R 31/31727 (2013.01) [G01R 31/31922 (2013.01); G01R 25/00 (2013.01); G01R 25/005 (2013.01); G01R 31/31937 (2013.01); H03K 5/1565 (2013.01); H03K 5/19 (2013.01)] 17 Claims
OG exemplary drawing
 
6. A device, comprising:
a simple logic gate having a first input to receive a reference clock and a second input to receive a phase-shifted clock, wherein the simple logic gate generates a simple logic output signal having a duty cycle dependent on a phase difference between the reference clock and the phase-shifted clock, wherein the duty cycle of the simple logic output signal is unique for a first set of phase differences and ambiguous for a second set of phase differences;
a reset-set flip flop having a third input to receive the reference clock and a fourth input to receive the phase-shifted clock, wherein the reset-set flip flop generates a flip flop output signal having a duty cycle dependent on the phase difference between the reference clock and the phase-shifted clock, wherein the duty cycle of the flip flop output signal is unique for a third set of phase differences and ambiguous for a fourth set of phase differences; and
a low pass filter having an input to receive at least one of the simple logic output signal and the flip flop output signal, wherein the low pass filter generates an averaged output signal based on the at least one of the simple logic output signal and the flip flop output signal.