US 12,461,145 B1
Temporal lockstep
Elio Guidetti, Montano Lucino (IT); Filippo Grillotti, Milan (IT); Fabio Giuseppe De Ambroggi, Biassono (IT); Riccardo Tedeschi, Reggio nell'Emilia (IT); Davide Rossi, Bologna (IT); and Alessandro Nadalini, Crevalcore (IT)
Assigned to STMicroelectronics International N.V., Geneva (CH); and ALMA MATER STUDIORUM—UNIVERSITA' DI BOLOGNA, Bologna (IT)
Filed by STMicroelectronics International N.V., Geneva (CH); and ALMA MATER STUDIORUM—UNIVERSITA' DI BOLOGNA, Bologna (IT)
Filed on May 1, 2024, as Appl. No. 18/652,398.
Int. Cl. G01R 31/317 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G01R 31/31715 (2013.01) [G06F 9/30181 (2013.01); G06F 9/3802 (2013.01)] 20 Claims
OG exemplary drawing
 
15. A method comprising:
providing a processor core comprising a pipeline including an instruction fetch circuit and an instruction decode and execute circuit;
wherein the instruction decode and execute circuit comprises a controller including a finite state machine, wherein the finite state machine comprises a plurality of states to control the processor core;
providing a voting circuit configured to provide a control signal to control the finite state machine for transitioning from a current state of the plurality of states to a next state;
fetching, with the instruction fetch circuit, a first instruction;
generating a first dummy instruction based on the first instruction and a first real instruction based on the first instruction;
executing, with the instruction decode and execute circuit, a first dummy instruction to generate a first dummy result;
store the first dummy result in a first dummy buffer;
executing, with the instruction decode and execute circuit, the first real instruction to generate a first real result; and
comparing the first dummy result stored in the first dummy buffer with the first real result to identify an error.