| CPC G01R 31/2856 (2013.01) [G01R 31/2882 (2013.01)] | 20 Claims |
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1. A device for failure risk measurement in a semiconductor Integrated Circuit (IC), the device comprising:
a plurality of data-change pulse generators, each data-change pulse generator being configured, when a signal from a respective data path and/or control logic circuit of the semiconductor IC changes, to generate a pulse of a preset time duration on a respective output path, wherein the data paths and/or control logic circuits of the semiconductor IC have a common clock;
a signal combiner, configured to combine the output paths from the plurality of data-change pulse generators and provide a combined output path thereby;
an adjustable delay circuit, configured to delay a signal on the combined output path by a configurable time duration, providing a delayed combined output path signal thereby; and
a device state element, configured to receive the delayed combined output path signal at a data input, to be clocked by a signal based on the common clock and to output a failure risk measurement signal.
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