US 12,461,142 B2
Semiconductor wafer test system for controlling supply of power to semiconductor wafer test apparatus and method of controlling supply of power to semiconductor wafer test apparatus
Yong Hyun Kim, Seoul (KR); Jae Hoon Joo, Yongin-si (KR); Hyo Sang Jo, Uiwang-si (KR); and Ki Young Jeon, Yongin-si (KR)
Assigned to YC Corporation, Gyeonggi-do (KR)
Filed by YC Corporation, Seongnam-si (KR)
Filed on Jun. 12, 2023, as Appl. No. 18/333,209.
Claims priority of application No. 10-2022-0076861 (KR), filed on Jun. 23, 2022.
Prior Publication US 2023/0417824 A1, Dec. 28, 2023
Int. Cl. G01R 31/28 (2006.01)
CPC G01R 31/2851 (2013.01) 18 Claims
OG exemplary drawing
 
1. A semiconductor wafer test system comprising:
a test operating server configured to manage a wafer test schedule and send a request to switch to a waiting mode or to a ready mode to a semiconductor wafer test apparatus in accordance with the wafer test schedule; and
the semiconductor wafer test apparatus configured to switch to the waiting mode in response to receipt of the request to switch to the waiting mode from the test operating server and configured to switch to the ready mode in response to receipt of the request to switch to the ready mode from the test operating server, wherein
the test operating server is configured to send the request to switch to the waiting mode when a first lot of wafers to be tested is unloaded, and send the request to switch to the ready mode before loading of a second lot of wafers to be tested.