US 12,461,141 B2
Identifying failures in device cores
Howard Lin, Boston, MA (US); and Michael C. Panis, Somerville, MA (US)
Assigned to Teradyne, Inc., North Reading, MA (US)
Filed by Teradyne, Inc., North Reading, MA (US)
Filed on Mar. 21, 2023, as Appl. No. 18/124,466.
Prior Publication US 2024/0319261 A1, Sep. 26, 2024
Int. Cl. G01R 31/28 (2006.01)
CPC G01R 31/2841 (2013.01) [G01R 31/2856 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A system for testing a device under test (DUT), the DUT comprising a first core and a second core, the system comprising:
channels for connecting to a number of pins on the DUT, the channels for sending test data to the DUT and for receiving measurement data from the DUT based on the test data;
wherein the measurement data comprises time-division-multiplexed (TDM) data comprised of successive data packets received from the DUT over the channels as part of a bitstream, where each data packet comprises a first number of bits from the first core and a second number of bits from the second core, where the data packets are transmitted in time slots with each time slot corresponding to a transmission of the bitstream on the number of pins, and where the TDM data is repeated in a pattern on the channels every predetermined number of time slots; and
circuitry associated with the channels to compare the measurement data with expected data, and to determine pass/fail status for the first core and for the second core based on the comparison;
wherein the circuitry is configured to determine fail counts for the first core and for the second core based on the comparison, with a fail count indicating how many times that the first core or the second core has failed a test; and
wherein the circuitry is configured to limit storage of subsequently-received measurement data for the first core or for the second core when the fail count exceeds a threshold number for the first core or the second core.