US 12,461,042 B2
Automatic maverick wafer screening using die pass pattern
Iman Abdali Mashhadi, Kanata (CA); Regina Inyangat Akudo, Kanata (CA); and Syed Faizan-ul-Haq Gilani, Stittsville (CA)
Assigned to Infineon Technologies Canada Inc., Ottawa (CA)
Filed by Infineon Technologies Canada Inc., Ottawa (CA)
Filed on Nov. 28, 2023, as Appl. No. 18/521,732.
Prior Publication US 2025/0172503 A1, May 29, 2025
Int. Cl. G01N 21/95 (2006.01); G01N 21/88 (2006.01); G01N 21/956 (2006.01); H01L 21/66 (2006.01)
CPC G01N 21/9501 (2013.01) [G01N 21/8851 (2013.01); G01N 21/95607 (2013.01); H01L 22/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for automatically performing maverick screening of a semiconductor wafer, the method comprising:
acquiring an inspection pass status for each of a plurality of die on a subject wafer, the inspection pass status being whether the corresponding die passed or failed inspection;
for each of multiple zones of the subject wafer, comparing a pass/fail percentage of the die within the corresponding zone with an expected pass/fail percentage for the corresponding zone, the expected pass/fail percentage being dependent on a history of pass/fail percentages for previous dies in a same corresponding zone for previously screened wafers, the comparison resulting in a deviation between the measured pass/fail percentage of the corresponding zone and the expected pass/fail percentage of the corresponding zone; and
identifying the subject wafer as a maverick wafer if the deviation for a predetermined number or more of the multiple zones falls outside of a corresponding deviation tolerance for the respective zone.